Along with the development of low temperature poly-silicon (LTPS) technology, high PPI (pixel per inch) products have gradually become the mainstream. The defects of high-PPI products comprise the reduction of the storage capacitance area, and hence additional storage capacitance must be produced to compensate the reduced storage capacitance area. The corresponding countermeasure is to additionally arrange a shielding layer at the undermost layer of an array substrate and allow the shielding layer to be connected with a common electrode. In this way, the storage capacitance between the shielding layer and active layers is additionally used to compensate the reduced storage capacitance.
FIG. 1a is a structural planar view of an LTPS array substrate, and FIG. 1b is a sectional view of the LTPS array substrate. FIG. 1b is a structural sectional view of three areas. The three areas are a common electrode connecting area, a display area and a drive area from left to right in sequence.
The conventional process for manufacturing the LTPS array substrate comprises: depositing a shielding layer film on a substrate and forming a pattern of a shielding layer 201 by one patterning process; depositing an insulating buffer layer and an amorphous silicon (a-Si) layer on the substrate provided with the shielding layer; crystallizing a-Si into poly-silicon (p-Si) by a p-Si formation process; forming a pattern of an active layer by one patterning process; forming a gate insulating layer on the substrate provided with the active layer; forming a gate electrode on the substrate provided with the gate insulating layer, in which a gate electrode for a positive channel metal oxide semiconductor (PMOS) (PMOS gate electrode) in a drive area is formed by one patterning process, and boron ion (B) implantation is performed, and a gate electrode for a negative channel metal oxide semiconductor (NMOS) (NMOS gate electrode) in a display area and a drive area are formed by one patterning process again, and phosphorous ion (P) implantation is performed, and the gate electrode for PMOS and the gate electrode for NMOS are provided on the same layer; subsequently, forming an intermediate insulating layer on the substrate provided with the gate electrode for NMOS; forming through holes for connecting a source/drain electrode layer and the active layer by one patterning process, in which the through holes run through the intermediate insulating layer; forming a through hole for connecting the shielding layer and a source/drain electrode layer by one patterning process, in which the through hole runs through the intermediate insulating layer and the gate insulating layer; depositing a source/drain metal film on the substrate provided with the through holes for connecting the source/drain electrode layer and the active layer and the through hole for connecting the shielding layer and the source/drain electrode layer; and forming the source/drain electrode layer by one patterning process.
As the through holes for connecting the source/drain electrode layer and the active layer and the through hole for connecting the shielding layer and the source/drain electrode layer are formed by two patterning processes, the process is relatively complex. However, if two kinds of through holes are formed by one patterning process in order to simplify the process, as the through hole for connecting the source/drain electrode layer and the active layers and the through hole for connecting the shielding layer and the source/drain electrode layer have different depths, the required etching time periods are also different from each other, and hence the through holes for connecting the source/drain electrode layer and the active layers will be overetched and the through hole for connecting the shielding layer and the source/drain electrode layer will be not enough etched.